Office of Research, UC Riverside
Sheldon Tan
Professor
Electrical & Computer Eng
sheldont@ucr.edu
(951) 827-5143


SHF:Small: EM-Aware Physical Design and Run-Time Optimization for sub-10nm 2D and 3DIntegrated Circuits

AWARD NUMBER
009769-002
FUND NUMBER
33433
STATUS
Active
AWARD TYPE
3-Grant
AWARD EXECUTION DATE
5/21/2018
BEGIN DATE
8/1/2018
END DATE
7/31/2021
AWARD AMOUNT
$450,000

Sponsor Information

SPONSOR AWARD NUMBER
1816361
SPONSOR
NATIONAL SCIENCE FOUNDATION
SPONSOR TYPE
Federal
FUNCTION
Organized Research
PROGRAM NAME

Proposal Information

PROPOSAL NUMBER
18040582
PROPOSAL TYPE
New
ACTIVITY TYPE
Basic Research

PI Information

PI
Tan, Sheldon
PI TITLE
Other
PI DEPTARTMENT
Electrical & Computer Eng
PI COLLEGE/SCHOOL
Bourns College of Engineering
CO PIs

Project Information

ABSTRACT

Electro-Migration (EM) has emerged as a major design constraint and reliability issue for nano-meter-scale integrated circuits (ICs) and emerging three-dimensional (3D) stacked ICs. Due to its importance, many advances have been made recently in EM modeling and fast numerical assessment techniques. However, those advanced EM models have not been fully exploited by existing EM-aware physical design and optimization methods to reduce and mitigate the overly conservative VLSI design practices. The new EM models can naturally consider wire topology and structure impacts on the EM failures of interconnect wires and recovery effects of EM aging process for the first time, thus opening new opportunities for EM optimization at physical design stages. Novel EM optimization techniques to be explored in this award will improve IC reliability amid continued aggressive transistor scaling and increasing power density. The research in this project will contribute significantly to the core knowledge and technologies of EM-aware physical design and optimization for nano-meter VLSI designs. This investigator will seek to recruit underrepresented minority students to further contribute to the diversity in U.S. science and technology workforce.

This project will develop advanced EM-aware physical optimization techniques and run-time EM mitigation techniques for traditional two-dimensional (2D) and emerging 3D stacked ICs in the nano-meter regime. First, the research will develop new EM-aware optimization techniques for power delivery networks of mainstream 2D and emerging 3D ICs based on the newly proposed EM immortality-check rules for general interconnect trees. The new optimization algorithms will also consider the EM-induced aging effects for targeted lifetime optimization using more accurate EM lifetime estimation methods. Second, the research will explore the run-time recovery effects of the EM aging process to extend the EM lifetime of the signal and power/ground (P/G) networks in 3D stacked ICs. The new optimization methods will, thus, help extend the lifetime of the 3D stacked ICs.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
(Abstract from NSF)